A driving circuit used for a thin film transistor liquid crystal display (TFT-LCD) panel mainly includes a gate driving circuit and a data driving circuit, wherein the gate driving circuit applies an inputted clock signal onto a gate line of the liquid crystal display panel after converting the clock signal by a shift register. The gate driving circuit includes multiple stages of shift registers, each being connected to a corresponding gate line to output a gate diving signal. In the prior art, the multiple stages of shift registers of the gate driving circuit are connected to each other, an initial signal is inputted into a first stage shift register, an input terminal of an Nth stage shift register is connected to an output terminal of an (N−1)th stage shift register, and an output terminal of an (N+1)th stage shift register is connected to a reset terminal of the Nth stage shift register.
FIG. 1 is a schematic structure diagram showing a shift register in the prior art. As shown in FIG. 1, the shift register includes ten transistors M1 to M10 and a first capacitor C1 which are connected in the following manner: a gate of a first transistor M1 is connected to a first electrode thereof; a second electrode of the first transistor M1 is connected to a first electrode of a second transistor M2, a gate of a third transistor M3, a gate of a sixth transistor M6, a gate of a eighth transistor M8, a first electrode of a tenth transistor M10 and a first electrode of the first capacitor C1 at an node P1; a second electrode of the first capacitor C1 is connected to a second electrode of the third transistor M3 and a first electrode of a fourth transistor M4; a gate of the fourth transistor M4 is connected to a first electrode of a fifth transistor M5 and a first electrode and a gate of a ninth transistor M9; a second electrode of the fifth transistor M5 is connected to a first electrode of the sixth transistor M6 and a gate of the tenth transistor M10 at an node P3; a second electrode of the ninth transistor M9 is connected to a gate of the fifth transistor M5 and a first electrode of the eighth transistor M8 at an node P2.
The first electrode of the first transistor M1 is connected to an input terminal G(N−1) of the shift register, the second electrode of the first capacitor C1 is connected to an output terminal G(N) of the shift register. The gate of the second transistor M2 is connected to a reset terminal G(N+1) of the shift register. The first electrode of the third transistor M3 is connected to a first clock signal terminal CLK, the first electrode of the fifth transistor M5 is connected to a second clock signal terminal CLKB. The second electrodes of the transistors M2, M4, M6, M8 and M10 are connected to a low-level input terminal VSS of the shift register.
FIG. 2 is an operation timing diagram of the shift register shown in FIG. 1. As shown in FIG. 2, DATA represents a data signal. The detailed operating principle of the shift register is known in the prior art, and is not elaborated herein. However, with increasing demands for slim bezel and high resolution of a display panel in the market, the above shift register having a complex structure and poor performance could not meet the demands.